Testing memory for cryogenic quantum control systems

The challenge

In the future, quantum processors will be able to solve complex problems exponentially faster than any traditional computer. However, the challenges to make this leap from “classical” to “quantum” computing architectures are vast, featuring many interdisciplinary challenges ranging from quantum device physics to electronic control systems. SureCore is a UK company which develops and licenses low power memory solutions for use in System-on-Chip (SoC) devices. These pre-verified memories enable integrated circuit designers to confidently develop their SoC without additional prototyping and debugging iterations which are extremely costly. SureCore are expanding their product portfolio to include a range of memory solutions for scalable control of quantum computers. A key difference for quantum-oriented products is that they must operate at “cryogenic” temperatures, typically less than 5K. While SureCore’s new memory products have been designed to operate at these massively lower operating temperatures, empirical validation of their designs in a cryogenic environment is an essential step in validating both their functionality and performance. Lacking any cryogenic test facilities of their own, SureCore turned to NPL via the Analysis for Innovators (A4I) programme for help. This enabled them to verify a suite of memory products integrated on a custom designed test chip at extremely low temperatures.

The solution

NPL and SureCore developed a bespoke test probe and instrumentation system for efficient testing of the memory test chips at cryogenic temperatures. After first cooling the devices to 77K and subsequently 4.2K, detailed operational and performance tests could be undertaken. The test set up was designed to measure key memory parameters. This data was then analysed to check that it correlated with simulation results. This guarantees that when SoC designers use the memory simulation and timing models in their custom SoC design both functionality and performance will be identical in silicon.

Measurements of the static and dynamic electrical power were performed for multiple memory types. These tests are critical to understand and manage power requirements for integrated circuits in a cryogenic environment. A set of tests measured the maximum operating speed of each memory type. SoC designers use this information to ensure that their use of a particular memory remains within the practical speed limits for error-free device operation. NPL collected test data encompassing the full range of bias voltages and operating speeds for each of the various memory types on a test chip. Multiple test chips were evaluated allowing statistical information to be analysed. Measuring multiple test chips also gave information about the variability of the results across a given fabrication run. The comprehensive test results were then used to validate performance and timing data generated by simulation. These key parameters are captured in both memory product datasheets as well as simulation and timing models. Good correlation was found between simulated parameters and actual measurements.

The impact 

The test results and the subsequent correlation exercise will enable SureCore to license their cryogenic memory IP to SoC designers working on quantum control hardware. In addition to enabling the growth of their business, this will ultimately allow the control electronics to be migrated into the cryogenic environment alongside the qubits thereby facilitating quantum computer scaling.

Surecore digital memory chip mounted on circuit boards ready for low temperature testing.