National Physical Laboratory

Carbon Nanotube Interconnects

Figure 1: SEM micrograph of vertically aligned multiwall carbon nanotube arrays terminated at the top of the image with metal layers
Figure 1: SEM micrograph of vertically aligned multiwall carbon nanotube arrays terminated at the top of the image with metal layers


As the sizes of electronic circuits shrink, new material challenges have emerged. For example, copper suffers from electromigration as the dimensions of interconnects become smaller. Replacements for traditional materials commonly used in electronic circuits, such as copper, have to be found. Many different materials are being explored for replacing traditional materials at the nanoscale. These include graphene, carbon nanotubes, copper and silicon nanowires, silver nanoparticles, etc.

The Electronic Interconnects Group at NPL is working in collaboration with Surrey University in a project aimed at developing characterisation tools (mechanical, thermal and electrical) for nano-interconnects systems based on nano-carbon.

At NPL we are working on interconnect systems involving bonding carbon nanotubes to substrates using solder in order to exploit the superior electrical properties of carbon nanotubes (such as high current carrying capacity).

Nano-carbon interconnect fabrication process

A process has been developed for the synthesis and subsequent transfer of carbon nanotube arrays onto substrates (such as printed circuit boards) as shown in Figure 2:

Figure 2: Schematic of the interconnect manufacturing process showing (1) patterning of a silicon substrate with catalyst; (2) the PTCVD synthesis of MWCNT arrays; (3) the functionalisation process; (4) the metallisation process; (5) and (6) the CNT to Cu
Figure 2: Schematic of the interconnect manufacturing process showing (1) patterning of a silicon substrate with catalyst; (2) the PTCVD synthesis of MWCNT arrays; (3) the functionalisation process; (4) the metallisation process; (5) and (6) the CNT to Cu substrate bonding processes; and (7) and (8) a repeat of steps (3), (4) and (5) to give a finished interconnect


Carbon nanotube synthesis

Multi-walled carbon nanotubes (MWCNTs) are synthesised using a photo-thermal chemical vapour deposition (PTCVD) system at Advanced Technology Institute at the University of Surrey. The growth is carried out at CMOS compatible temperatures on photolithography patterned silicon substrates.

Carbon Nanotube Interconnects Figure 3a Carbon Nanotube Interconnects Figure 3b
Figure 3: (a) SEM micrograph showing MWCNT arrays produced by PTCVD on a silicon support substrate; and (b) TEM micrograph of MWCNTs synthesised by PTCVD showing details of their structure


These columns are 200um high, and such interconnect systems are very flexible in shear, and are expected offer good reliability from CTE mismatch considerations.

MWCNT functionalisation

Carbon nanotubes only bind to other materials and themselves with weak forces. As a results the surface of the MWCNTs have to be conditioned in order to allow stronger bonds to be formed. Stronger adhesion to other materials is essential for better interconnects.

Metallisation

The metallisation process is a key step in the interconnect manufacturing process. The metallisation of the tip of the CNTs is carried out using either electron beam evaporation or magnetron sputtering. The choice of metals used is critical to getting strong adhesion of the CNTs for bonding with substrates.

Figure 4: Vertically aligned multiwall carbon nanotubes with metallised tips
Figure 4: Vertically aligned multiwall carbon nanotubes with metallised tips


The bonding process

The metallised MWCNTs can subsequently be bonded to common substrates used in electronics industry using solder or sintered silver materials and is carried out at CMOS compatible temperatures.

Figure 5: Voltage as a function of current graph of two different MWCNT interconnects showing their ohmic characteristics
Figure 5: Voltage as a function of current graph
of two different MWCNT interconnects showing
their ohmic characteristics
Figure 6: SEM micrograph showing MWCNT arrays with metal layers on top and bottom bonded to a copper substrate
Figure 6: SEM micrograph showing MWCNT
arrays with metal layers on top and bottom
bonded to a copper substrate


Electrical characterisation by 4-probe techniques show that the interconnects have ohmic characteristics. However, resistance values obtained for the interconnects are currently higher than expected due to a mismatch between the electrical properties of the materials used in the bonding of MWCNTs, and this is currently the subject of further research.

High temperature performance

Interconnects were tested up to 300 °C in air and were found to retain their electrical performance as shown by the graph below:

Figure 7: Voltage as a function of current graph of an MWCNT interconnect showing ohmic characteristics at both room temperature and 300 °C
Figure 7: Voltage as a function of current graph of an MWCNT interconnect showing ohmic characteristics at both room temperature and 300 °C


Due to the flexibility of the MWCNTs, the interconnects are expected to perform well for applications where TCE mismatch between substrate and components are an issue.

Summary

A method of fabricating interconnects which is both scalable and cheap to implement for large scale packaging applications is proposed. We have developed a functionalization process for MWCNT attachment to substrates giving good electrical and thermal performance. Electrical measurements showed resistance was dominated by contact resistance. Thermal performance has been proven up to 300 °C for extended periods.

Last Updated: 9 Sep 2015
Created: 9 Sep 2015

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